This application claims the priority benefit of Taiwan application serial No. 87109990, filed Jun. 22, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
The invention relates to an Ethernet element, and more particularly to an Ethernet switch.
2. Description of Related Art
Currently, Ethernet, a most common Local Area Network (LAN), has been used in information communication network market. In early time, the structure of Ethernet was implemented by means of 10BASE5, called a Bus Topology Network. Furthermore, 10BASE2 is a cost-saving and revised form of the 10BASE5.
Although the 10BASE2 is also a Bus Topology Network and operates at a frequency of 10 MHz, a coaxial cable used has different properties and the maximum of transmission length is limited to less than 200 m. There are many disadvantages exiting in the structure of the 10BASE5 or 10BASE2. For example, cost for installing is higher; the installing for the 10BASE5 or 10BASE2 network is inflexible; and distribution line systems in buildings can not be effectively used. To solve the disadvantages mentioned above, 10BASE-T, a Star Topology Network system established by use of twin-stranded wires, is used.
The larger the structure of Local Area Network is, the more the amount of transmitting on the Local Area Network will be. When the number of nodes for connections on the Local Area Network is increased, the efficiency of the Ethernet is decreased. In order to satisfy the requirements of the large structure of the Local Area Network or high-speed data terminal equipment, a high-speed Ethernet operating at a higher frequency is provided. The high-speed Ethernet which operates at a frequency of 00 MHz, further enhances the functions of the Ethernet network 10BASE. In the high-speed Ethernet, a media independent interface (MII) is defined. Therefore, the high-speed Ethernet can be connected to another network, such as 100BASE-TX, 100BASE-T4 or 100BASE-FX, by using twin-stranded wires or fiber optical cables via network nodes.
Basically, the 10BASE5, 10BASE2, 10BASE-T, 100Base-TX, 100BASE-T4 or 100BASE-FX is a sharing bandwidth network system. All connected nodes on the network system can share the bandwidth thereof. The bandwidth of the network system 10BASE is 10 MHz while the bandwidth of the 100BASE is 100 MHz. When the number of the nodes connected is over a threshold value, the performance of the sharing network system reaches a best condition. A segmenting methodology, different from the method of accelerating operating pulse frequency, is used to improve the functions of the Ethernet system. The segmenting methodology segments the entire network system into several separated sub-networks. Each separated sub-network is located within a different range of collision domain. Nodes connected to different sub-networks are unable to share the bandwidths of the sub-networks with each other. If the network system is not segmented, each node of the Local Area Network 100BASE having 100 share nodes can share a bandwidth of 1 MHz only. However, if the system having 100 nodes is divided into 2 segments, each node of the Local Area Network 100BASE can share a bandwidth of 2 MHz. A segmented Local Area Network system having an Ethernet protocol is also called a switched Ethernet. Packets transmitted between the two segments of the network system are switched by use of an Ethernet switch. The Ethernet switch is used to switch packets between different segments of the local Area Network system. Packets transmitted from one segment to another segment is forwarded, but packets in the same segment transmitted from one node to another node will not be switched. These prior arts all are disclosed in U.S. Pat. No. 5,274,631, 5,491,694 and 5,588,151.
FIG. 1 is a circuit block diagram showing an Ethernet switch having a distribution memory structure according to the prior art.
Referring to FIG. 1, the prior Ethernet switch includes at least a switching IC 10 and a plurality of port ICs 11a, 11b and 11c. The switching IC 10 is used for data switching and transmitting control of each port. Each port IC has a memory. For example, the IC port 11a has a built-in memory 12a which is used to store and switch packet data. In the structure of the switch, when network data are transmitted from a port 13a to a port 13c, the data must be first stored in the memory 12a and then stored in a memory 12c. As shown in FIG. 1, the size of the memory of each port IC must have been previously decided when designed. Since any port of the network switch is likely connected to a Local Area Network, such as 10BASE5, 10BASE2, 10BASE-T, 100BASE-TX, 100BASE-T4 or 100BASE-FX, with a different specification, each port IC should be given a larger storage capacitance of memory for being suitable for different specifications. Therefore, more memory consumption is caused. Furthermore, data transmission must be implemented through two memories, such that the efficiency of the network switch is decreased.
In view of the above, the first object of the invention is to disclose a function of connecting a network system 10BASE to a network system 100BASE, thereby extending the uses of the old system to new system.
The second object of the invention is to disclose an Ethernet switch having a share memory structure for saving required memories of the switch.
In addition, the third object of the invention is to disclose a method for accomplishing the functions, of the switch. The method includes: sharing memory; storing a packet buffer pool; handling packet buffer pool congestion; and switching network packets.
According to the invention, the Ethernet switch having a share memory structure is provided for selectively transmitting network packets. The switch includes: a memory device, a memory controller, a data switching controller and more than two network ports. Furthermore, the memory device provides network packet accesses and stores routing data. The memory controller is coupled to the memory device for managing/controlling network packets in the memory device. The data switching controller is coupled to the memory controller for packet routing/learning. Each network port is coupled to the memory controller and data switching controller. The Ethernet switch of the invention has an advantage of saving required memories thereof.
The main object of the invention is to provide an Ethernet switch having a share memory structure for selectively transmitting network packets. The switch includes: a routing table; a packet buffer; a share memory access controller; a data switching controller; more than two network ports; and a buffers manager. Moreover, the share memory access controller coupled to the routing table and the packet buffer consists of a means for arbitrating, a means for data multiplexing, a means for addressing, and a means for access command controlling. The data switching controller coupled to the share memory access controller consists of a means for initializing, a means for arbitrating and a means for aging the routing table, and network routing/learning. Each network port is coupled to the share memory access controller and the data switching controller. The buffer manager is coupled to each network port. The buffer table is coupled to the buffer manager. The routing table is used to store routing data of packets by means of the share memory access controller. The packet buffer accepts packet accesses requested by each network port by use of the share memory access controller. The buffer table records the use statuses of the packet buffer by means of each network port and the share memory access controller. The buffer manager learns the use statuses of packet buffer in virtue of each network port and the share memory access controller, thereby managing the packet buffer.
According to a preferred embodiment of the invention, a memory device includes a routing table and a packet buffer. The routing table coupled to a memory controller is used to store routing data of a data switching controller via the memory controller. The packet buffer coupled to the memory controller is used to accept packet accesses requested by each network port via the memory controller.
According to a preferred embodiment of the invention, the memory controller includes a memory interface and a memory manager. The memory interface coupled to the memory device, data switching controller and each network port is used to control the accesses of the memory device. The memory manager coupled to each network port is used to manage the memory device by means of the memory interface.
According to another preferred embodiment of the invention, a memory manager includes a buffer table and a buffer manager. The buffer table records the use statuses of the memory device by means of each network port and a memory interface. The buffer manager is coupled to the buffer table for learning the use statuses of packet buffer, thereby managing the packet buffer.
According to a further embodiment of the invention, a data switching controller includes a routing controller and a learning controller. The routing controller is used for packet routing of each network port. The learning controller is used to store packet routing data by means of the memory controller.
According to a preferred embodiment of the invention, the routing controller selectively selects a corresponding network port in response to the destination address data of received packets. In addition, the learning controller selectively selects a corresponding network port in response to the source address data of received packets.
According to one more embodiment of the invention, each network port includes an Ethernet communication protocol controller and a packet data access controller. The Ethernet communication protocol controller mainly accomplishes all functions specified by IEEE 802.3 section 4. The packet data access controller is used to receive and transmit packets.
According to a preferred embodiment of the invention, the Ethernet communication protocol controller includes a media independent interface, a reconciliation sub-layer and a media access controller. The media access controller has the functions of receiving and transmitting which meet the specifications of IEEE 802.3 section 4.
According to a preferred embodiment of the invention, the packet data access controller includes a receive direct memory access controller and a transmit direct memory access controller. The receive direct memory access controller is used to receive packets. The transmit direct memory access controller is used to transmit packets.
Another object of the invention is to provide a method for buffering and managing an Ethernet switch. The Ethernet switch includes a memory consisting of a routing table, a buffer manager and a plurality of network ports each of which includes a receive direct memory access controller and a transmit direct memory access controller. The method includes segmenting the memory device into a plurality of segments each of which is assigned with a buffer ID representing a corresponding packet position in the memory device; maintaining the linked list of buffer IDs by the buffer manager and dynamically assigning a buffer ID to each forwarded packet; assigning unused buffer IDs to the receive direct memory access controller by the buffer manager; and retrieving the buffer IDs from the transmit direct memory access controller by the buffer manager.
According to a preferred embodiment of the invention, the method further includes assigning a buffer ID by the receive direct memory access controller when any one of the network ports receives a packet; and selecting the corresponding transmit direct memory access controller of the network port to transmit the packet according to the buffer ID corresponding to the packet if the packet is to be forwarded.
According to another embodiment of the invention, the method further includes performing a congestion control, wherein if the sum of the number of packets remaining to reach a minimum of threshold value for each packet port where the number of transmission-waiting packets does not reach the minimum of threshold value is larger or equal to a predetermined value, the other network ports in each of which the number of transmission-waiting packets is larger or equal to a minimum of threshold value are prevented from increasing the number of transmission-waiting packets by the congestion control.
According to one more embodiment of the invention, the method further includes performing a congestion control, wherein the number of transmission-waiting packets of any one of the network ports is larger or equal to a maximum of threshold value, the network port is prevented from increasing the number of transmission-waiting packets by the congestion control.
One more object of the invention is to provide a method for buffering and managing an Ethernet switch. The Ethernet switch includes a memory consisting of a routing table and a packet buffer, a buffer manager and a plurality of network ports each of which includes a receive direct memory access controller and a transmit direct memory access controller. The method includes establishing a Free-List by presenting the packet buffer in a form of linked list, wherein a Free-Header register is used to point out the header index of the unused packet buffers and a Free-Tail register is used to point out the tail index of the unused packet buffers; transmitting the buffer index of the Free-Header register to the interface of a corresponding receive direct memory access controller when the interface of each receive direct memory access controller emits a packet buffer request; then, adding the buffer index of the interface of the receive direct memory access controller to the tail of a transmitting linked list of the network port when each packet switching operation is performed; sending the buffer index in the Head register of a TX-List to the interface of the transmit direct memory access controller if the FX-List is not empty when each transmit direct memory access controller emits a packet transmitting request; and retrieving the buffer index of the interface of the transmit direct memory access controller back to the Free-Tail register when each transmitting operation is completed and then informing the transmit direct memory access controller that retrieving is completely finished.
According to a preferred embodiment of the invention, the method further includes performing a congestion control, wherein if the sum of the number of packets remaining to reach a minimum of threshold value for each network port where the number of transmission-waiting packets does not reach the minimum of threshold value is larger or equal to a predetermined value, other network ports in which the number of transmission-waiting packets is larger or equal to a minimum of threshold value are prevented from increasing the number of transmission-waiting packets by the congestion control, and the buffer index of the Free-Header register is no longer transmitted to the interfaces of receive direct memory access controllers corresponding to the network ports until this condition disappears.
According to one more embodiment of the invention, the method further includes performing a congestion control, wherein the number of transmission-waiting packets of any one of the network ports is larger or equal to a maximum of threshold value, the network port is prevented from increasing the number of transmission-waiting packets by the congestion control.